LISA { Machine Description Language for Cycle - Accurate Models ofProgrammable DSP
نویسندگان
چکیده
{ This paper presents the machine description language LISA for the generation of bit-and cycle accurate models of DSP processors. Based on a behavioral operation description, the architectural details and pipeline operations of modern DSP processors can be covered. Beyond the behavioral model, LISA descriptions include other architecture-related information like the instruction set. The information provided by LISA models enables automatic generation of simulators and assemblers which are essential elements of DSP software development environments. In order to proof the applicability of our approach, a realized model of the Texas Instruments TMS320C6201 DSP is presented and derived LISA code examples are given.
منابع مشابه
Leon Processor Architecture Implementation with LISA
This paper presents the machine description language LISA for the generation of bit and cycle accurate models of LEON processors. Depending on a behavioral operation description, the architectural specification and pipeline operations of modern LEON processors can be successfully implemented. The behavioral model LISA of includes other architecture related information like the instruction set. ...
متن کاملA survey on modeling issues using the machine description language LISA
This paper presents a survey on modeling issues of programmable architectures using the machine description language LISA. Various architectures presenting diverse architectural characteristics will be presented and the feasibility of automatically generating simulator, assembler, linker and graphical debugger frontend will be discussed. The presented approach is not limited to a fixed abstract...
متن کاملA Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools
Many ISA-level machine description languages have been introduced to support the automated development and retargeting of digital signal processor (DSP) software development tools. These languages have yet to move below the ISA-level and adequately address DSP pipeline issues. ISA-level bit-accurate models may be reasonable for small micro-controllers, but are inadequate when applied to complex...
متن کاملBPDL – Machine Description Language For Clustered VLIW Processors
Recent families of Digital Signal Processors show a VLIW-like architecture. These processors comprise of multiple execution units agglomerated into several data paths. With heavily pipelined, atomic RISC like operations, these are able to execute several instructions in a single cycle. The scheduling is done statically, and this saves hardware at the expense of more sophisticated compiler. This...
متن کاملThe RAMP Architecture & Description Language
The RAMP (Research Accelerator for Multiprocessors) project is developing infrastructure to support high-speed emulation of large scale, massively parallel multiprocessor systems using FPGA platforms. In this paper, we describe our proposal for a RAMP Design Framework (RDF), which has a number of challenging goals. The framework must support both cycle-accurate emulation of detailed parameteriz...
متن کامل